Non-volatile memory devices, such as flash memory devices or removable storage cards that hold data between power cycles, may use memory cells in which multiple bits of data may be written, called multi-level cell (MLC) flash memory. An example of a common mode of operation is that the flash memory system receives first data to be written into the flash from an external host. The flash memory system may write the first data into the flash, verify that the data can be reliably decoded, and then signal to the host that it is ready to accept new data and the host does not need to maintain the first data any longer. The writing rate of the system may depend on the time it takes the flash to write a given data in a reliable way.
In MLC flash systems, the data bits may be written to the memory cell in multiple passes, such that each pass overrides the previous pass, and typically the data can be reliably decoded only after the last pass is complete. (Writing the same data in several passes is one of the measures taken by the flash controller to minimize the effects of cross coupling from neighboring cells). In some cases only the Most Significant Bits (MSBs) may be written during the first pass, such that after the first pass the cell is partitioned in a very coarse way between a low state and a high state. The MSBs may suffer from unreliability due to insufficient programming pulses, and cross-coupling from data bits written afterwards. This situation may be corrected in the second pass when all bits are written. In another case all the data may be written in the first pass (or passes), but in a coarse manner, thus suffering from a high error rate. Then in the last pass the programming of the data is refined, thus resulting in low error rate, ensuring that the data can be recovered with high probability by using the available Error Correction Code. However, in both cases, if the writing of the data bits is interrupted before all of the passes are completed or before each of the portions of the memory cell is written, such as by a power failure, correctly decoding the data may be difficult.
Waiting for the full process to complete and only then signaling to the host to send new data may decrease significantly the writing rate of the flash. One approach to potentially avoid postponing the host from sending new data involves configuring the memory device to include a cache in which the data is fully written to the cache in a single pass. The cache may typically be comprised of memory cells which can be written faster and with a higher reliability than the cells intended for writing the data. For example, the cache cells may be single-level cells (SLCs) that are configured to write only one bit per cell, as contrasted with other flash cells in the memory device that may be configured to write multiple bits per cell. When using a cache, if the writing of the data in multiple passes or portions is interrupted, the data can be retrieved from the cache. However, using a cache involves adding an additional step of writing each element of data. Further, writing the data to cache results in enhanced wear on the cache that may limit the usable life of the memory device. Moreover, if every string of data to be written in the device is first written in the cache, an appreciable portion of the device may have to be devoted to the cache.